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AgendaPower Dissipation in CMOS
Low Power Design Challenges
Introduction to UPF
UPF & CPF
Advantages of UPF
F.I Vs P.I
Low Power Design and Verification Flow
Basic Terminologies
Power Management Architecture & Cells
Power Management Techniques
Implementation of UPF
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Power Dissipation in CMOS
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Low Power Design Challenges
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Basic Idea
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What is UPF?
Unified Power Format
UPF provides the ability for electronic systems to be designed with
power as a key consideration early in the process.
Why UPF?
No existing HDL adequately supports the specification of power
distribution and management.
Vendor-specific formats are non-portable and create opportunitiesfor bugs via inconsistent specifications.
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The Unified Power Format (UPF)
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Working Group Entity Members
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Fast Response to Industry Need
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UPF & CPF :-
These are the two power-formats that are recognized through-out
the industry which specifies power-gating considerations for a design.
Low power Cells which are specified in the UPF or CPF are inserted
separately in the netlist.
Power Compilers (Cadence RC who works on CPF ) and (Synopsys DC
which works on UPF) than reads the power intent and insert the low
power cells in the netlist. Thus at GLS it can be checked that power-
domains are following the power-up and power-down sequence
correctly.
UPFIEEE standard and 1.0, 2.0 are currently available.
CPF Maintained by Si2 group and versions 1.0, 1.0e, 1.1 and 2.0 are
currently available.
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Advantages of UPF:-
>The UPF file is the input to several tools (e.g., simulation,
synthesis, formal verification, and place-and-route tools).
>Synthesis tools can read the RTL/UPF design input files and
produce a netlist.
>The UPF file may be reused without change later in the tool flow.
>A UPF specification can be included with the other deliverables of
intellectual-property (IP) blocks and reused along with the other
delivered IP files.
>The same standard can be used in a multi-vendor tool flow.
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Functional Intent Vs Power Intent
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Low Power Design and Verification
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Few Terminologies :-
Operating corner
Power Domain
Power mode
Power Switch Rule
State Retention Rule
Power Switch Cell
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Power Management Architecture:-
Power States and Transitions
Isolation and Level Shifting
State Retention
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Isolation Cells :-
Isolation cells are typically used to protect logic that is powered onfrom logic that is powered off.
Used to prevent unknown values in unpowered logic from propagating
into live logic
Can also be used to prevent leakage current from live logic from
improperly powering unpowered logic.
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Level Shifters :-
Changes the voltage from one discrete value to another discrete value.
A 1b1 driven by 1.0 logic may be too much for 0.7 logic and likewise a
1b1 from 0.7 logic may not translate into 1b1 for 1.0 logic.
A Level Shifter changes a 0.7V 1b1 so you are propagating valid digitalvalues through the circuit.
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State Retention :-
A Sequential element that can retain its value despite being powered
off.
Useful to recover the last known state of the design when power was
removed.
Reduces the amount of time needed reset a design to a specific state to
continue operation.
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Power Management Techniques:-
Power Gating
Multi-Voltage
Dynamic voltage and frequency scaling
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Power Gating:-
Power reduction technique to reduce leakage power by shutting-
off , or powering down unnecessary logic.
Can be enabled by power switch or MTCMOS cells.
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Sleep Transistor used in Power Gating
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Multi Voltage:-
Power Saving Technique to operate different logic blocks atdifferent voltages.
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Bias Voltage:-
Used to change the threshold value of the cell to improve the
leakage characteristics of the cell.
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Dynamic Voltage and Frequency Scaling:-
Power saving technique to change the voltage/or clock frequencywhile the chip is running .
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Results
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Multi-Voltage Special Cells Requirement
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