VHDL(Iniciar)
Transcript of VHDL(Iniciar)
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INTRODUCCIÓN AL
LENGUAJE VHDL
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ÍNDICE.
1. Introducción.
2. Conceptos básicos del lenguaje y Aplicaciones.
3. Tipos de datos y Señales.4. Sentencias concurrentes y secuenciales. 5. Registros y máquinas de estados finitos.
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Bibliografía:
- VHDL Lenguaje estándar de diseño electrónico. Lluís Terés, Yago Torroja, Serafín Olcoz, Eugenio Villar. Ed, Mc Graw-Hill, 1998
- VHDL Modeling for Digital Design Synthesis
Yu-Chin Hsu, Kevin F. Tsai, Jessie T. Liu, Eric S.Lin. Ed, Kluwer Academic Publishers, 1995
- Hardware Design and Simulation in VAL / VHDL.
Larry M. Augustin, David C. Luckham, beniot A. Gennart, Youmth Huh, Alec G. Stanculescu. Ed, Kluwer Academic Publishers, 1991.
- VHDL Designers Reference.
Jean Michel Bergé, Alain Fonkova, Serge Maginot, Jacques Rovillard. Kluwer Academic Publishers, 1992
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INTRODUCCIÓN.
• Circuitos integrados. • Evolución del diseño electrónico• El lenguaje VHDL
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CIRCUITOS INTEGRADOS
• Un Circuito Integrado (C.I.) es un circuito electrónico donde tanto los componentes como su conexionado se construyen en un mismo dado de material semiconductor (Si)
chip
• 1958 J. Kilby (Texas Instr.) primer C.I.
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• Rápida evolución:Componentes SSI → Procesador VLSI
• Circuitos más complejos • Metodologías nuevas de diseño• Herramientas nuevas de diseño• Desarrollo paralelo
Microelectrónica ↔ Informática
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PROCESO BÁSICO DE DISEÑO
Requisitos y especificaciones
DiseñoArquitectural (RTL )
Diseño Lógico(puer tas)
Diseño Físico(transistores-layout)
Diseño Funcional
Fabr icacióny Test
Modeladoy
Síntesis
Configuración del PLD
Programación del PLDy Test
Altera
Diseño modelo VHDL
Simulación
Compilación
Análisis de Timing
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• Estas etapas son función de las distintas alternativas de diseño.
• Por analogía PROGRAMACIÓN se busca
SÍNTESIS DE ALTO NIVELChip desde una descripción de alto nivel
• Imprescindible los lenguajes HDL-- VHDL
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Síntesis de hardware
Proceso de Transformación de una descripción funcional de un circuito en una descripción estructural:
–Nivel de Transferencias entre registros.–Layout (Caso Ideal)
Síntesis
processbegin
for I in 0 to 10 loop:::
end loop;end process;
descripción funcionaldescripción funcional
descripción estructuraldescripción estructural
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Sintesis de Alto Nivel
• Func ión Objetivo : Una función de :– Estimación del área.– Retardos del Circuito
• Restricc iones : Condiciones que debe cumplir el circuito. (p.e. Area estimada < X. Retardo < Y...)
Síntesis
processbegin
for I in 0 to 10 loop
:::end loop;
end process;
Restricciones
FunciónObjetivo
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1.Aplication and laguage Introduction
- What is VHDL ?- Aplication areas- Limitations of VHDL- VHDL styles- Main laguages concepts- Entity- Architecture- Hierarchy- Declaration- Processes and types- Packages
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What is VHDL?
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Limitations
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VHDL Styles
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Entity
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Architecture
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Processes
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Types
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The package
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2. Signals and Data Types- The concept of a type- Standard data types- Assignments to signals- Type definition- Multi valued logic- Standard Logic- Using Standard Logic
VHDL Operators- Logical Operators- Relational Operators- Arithmetic Operators
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Type definition
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Type definition
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Type concept and specification
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Type std_logic is (
‘ U’, Uninitiliced
‘ X’ Unknown
‘ 0’ Logic 0
‘ 1’ logic 1
‘ Z’ high impedance
‘W’ Unknown
‘ L’ logic 0
‘ H’ logic 1
‘ _ ‘ Don´t care
Strong drive
Weak drive
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library IEEE;
use IEEE.Std_logic_1164.all;
entity MULS is
port ( A, B, : in std_logic ;
Z : out std_logic );
end MULS;
Using Standard Logic
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OPERADORES EN VHDL
Existen 3 tipos predefinidos:
• Operadores lógicos
• Operadores matemáticos
• Operadores relacionales
Por defecto, cada operador puede usarse con cierto tipo de datos.
El usuario puede definir funciones si precisa usar otros tipos.
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OPERADORES LÓGICOS
Son los siguientes:
• AND, NAND, OR, NOR
• XOR, XNOR
• NOT
• Además de desplazamientos lógicos/aritméticos izda/dcha y rotaciones: SLL, SRL, SLA, SRA, ROL, ROR.
Todos misma prioridad (de izda a dcha) salvo NOT que es siempre prioritaria.
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OPERADORES LÓGICOSTipos para los que están definidos:
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library IEEE;use IEEE.Std_logic_1164.all;entity MULS is
port ( A, B, : in std_logic ;Z : out std_logic );
end MULS;
architecture EX of MULS isbegin
z <= A and not (B or C );end EX;
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Signal A_BUS, B_BUS, Z_BUS:
std_logic_vector ( 3 downto 0 );
Equivalente a
ZBUS(3) <= A_BUS(3) and B_BUS(3);
ZBUS(2) <= A_BUS(2) and B_BUS(2);
ZBUS(1) <= A_BUS(1) and B_BUS(1);
ZBUS(0) <= A_BUS(0) and B_BUS(0);
Z_BUS <= A_BUS and B_BUS;
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OPERADORES RELACIONALES
Son los siguientes:
• igual (=) , distinto (/=)
• mayor(>), mayor o igual (>=)
• menor(>), menor o igual (>=)
Los operandos pueden ser de cualquier tipo.
El resultado es de tipo boolean.
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OPERADORES ARITMÉTICOS
Son los siguientes y para los tipos de datos indicados:
• suma (+), resta (-) --- cualquier tipo numérico
• producto (*), división (/) --- entero/real
• potencias (**) --- entero/real (exponente entero)
• módulo (mod), resto (rem) --- enteros
• valor absoluto (abs) --- entero/real
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CONSTANTES
Es un objeto que almacena un único valor durante toda la simulación
Ejemplos:
• constant E:real:=2.7172;
• constant V37:bit_vector (7 downto 0):= “0100110”;
• constant delay:time:=2ns;
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Arrays...
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3 2 1 0
1 2 3 4
z
c
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Concatenation and aggregates
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3. Concurrent and secuential Statements
- Concurrent Assignment Statements- The Process- Process execution- Sensitivity lists- The if statement- The case statement-The for loop-Variables
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• Es una sentencia concurrente que permite realizar asignaciones condicionales de valores, expresiones u objetos a señales.
• Sintáxis :[etiqueta:]señal<= valor1 when condición1 else
valor2 when condición2 else…………valorn when condiciónn elseunaffected;
SENTENCIA WHEN ... SELECT
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• Es una sentencia concurrente que permite realizar asignaciones condicionales de valores, expresiones u objetos a señales (análoga a WHEN..SELECT).
• Sintáxis :[etiqueta:]with expresión select
señal<= valor1 when resultado1 elsevalor2 when resultado2 else
…………valorn when resultadon elseunaffected when others;
SENTENCIA WITH... SELECT
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Process execution
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Sensitivity Lists
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The If Statement
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'ZGEWVGU HKTUV�VTWG�DTCPEJ
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The Case Statement
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The For Loop
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Variable usage
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4 ODDA ( 3 downto 0 )
Process (A)
variable TMP : std_logic;
begin
TMP:= ‘0’;
for I in A’low to A’high loop
TMP := TMP xor A(I);
end loop;
ODD <= TMP;
end p rocess ;
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ARQUITECTURA ESTILOS DE DESCRIPCIÓN
• La arquitectura define la funcionalidad de la entidad.
• Estilos de descripción:– Algorítmico: mediante un conjunto de
instrucciones que se ejecutan secuencialmente (proceso)
– Flujo de datos: mediante funciones u operadores.– Estructural: conjunto de componentes
interconectados
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Tema 4: Synthesis Issues
- Specifying registers in VHDL- Detecting a rising clock- Controling transparent latches- Finite State Machines
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Specifying registers inVHDL
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Entiti Flop is
port (D, Clk : in std_logic;
Q : out st_logic);
end Flop;
architecture A of Flop is
begin
process
begin
wait until Clk’event and Clk = ‘1’;
Q <= D;
end process;
end A;
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entity incomp_if is
port (EN, D : in std_logic;
Q : out st_logic);
end incomp_if;
architecture A of incomp_if is
begin
process (EN, D )
begin
if ( EN = ‘1’ ) then ;
Q <= D;
end if ;
end process;
end A;
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Controling Transparent Latches
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FINITE
STATE
MACHINES
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Reset*
E2
E0
E1
E3
S2 S1
S1,S0
X
X
Y
1 0
01
0
1
EJEMPLO
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Architecture una of UC is
signal EST_PRES,EST_SIG: integer range 0 to 3;
begin...........
EST_SIGEST_PRES
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SEC: process (EST_PRES, X,Y)--- inicialización
case EST_PRES is
when 0 =>if X= ‘0’ then EST_SIG<=1;
else EST_SIG <=2;
end if;
when 1 => EST_SIG<=3; when 2 =>
if Y= ‘1’ then EST_SIG<=3;
else EST_SIG <=2;end if;
when 3 =>
if X= ‘0’ then EST_SIG<=1;
else EST_SIG <=0;end if;
end case;
end process SEC;
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REG: process (clk, Reset)
begin
if Reset=‘0’ then EST_PRES <= 0;
if clk’ event and clk=‘1’ then
EST_PRES <= EST_SIG;
end if;
end process REG;
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S2 <=‘1’ when EST_PRES=2 else 0;
S1 <=‘1’ when (EST_PRES=1 or (EST_PRES=2 AND Y=‘1’)) else 0;
S0 <=‘1’ when (EST_PRES=2 AND Y=‘1’) else 0;
ESTADO <= EST_PRES;
outputs
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DESCRIPCIÓN COMPLETA:architecture una of UC is
signal EST_PRES,EST_SIG: integer range 0 to 3;begin
SEC: process (EST_PRES, X,Y)--- inicializacióncase EST_PRES is
when 0 =>if X= ‘0’ then EST_SIG<=1; else EST_SIG <=2;end if;
when 1 => EST_SIG<=3; when 2 =>
if Y= ‘1’ then EST_SIG<=3; else EST_SIG <=2;end if;
when 3 => if X= ‘0’ then EST_SIG<=1; else EST_SIG <=0;end if;
end case;end process SEC;
REG: process (clk, Reset)begin
if Reset=‘0’ then EST_PRES <= 0;if clk’ event and clk=‘1’ then
EST_PRES <= EST_SIG;end if;
end process REG;S2 <=‘1’ when EST_PRE else 0;S1 <=‘1’ when (EST_PRES=1 or (EST_PRES=2 AND Y=‘1’)) else 0;S0 <=‘1’ when (EST_PRES=2 AND Y=‘1’) else 0;ESTADO <= EST_PRES;
end una;
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Lógica combinacional
Registro
Generar estado
siguienteEntradas
Señales salida
Estado siguiente
Clk
Estado presente
Generar señales de
salida
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(activar overflow)
INIC SUM
LDR
OVF<--0CLR
SUM +INIC
OVF<--0CLR
OVF<--1
Cout
E0 (00)
E3(11) E1(01)
E2(10)
RESET*
01
0
1
0
1
01
0
1
INIC
(cargar elregistro)
(borrar registro yoverflow)
(borrar registro yoverflow) borrar sumar
EJEMPLO:
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library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity p1_ucV is
port( CLK ,RESETL : in std_logic;
INIC, SUM, COUT : in std_logic;
CLRL, LDRL, OVF1, OVF0L: out std_logic;
ESTADO : out integer range 0 to 3);
end p1_ucV;
Descripc ión en VHDL:
![Page 122: VHDL(Iniciar)](https://reader034.fdocuments.mx/reader034/viewer/2022042601/5452c5afb1af9f7c318b5308/html5/thumbnails/122.jpg)
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architecture UC of p1_ucV is
signal EST_PRES, EST_SIG_EST integer range 0 to 3;
begin
ES: process (EST_PRES, INIC,SUM,COUT)
begin
EST_SIG <= EST_PRES;
case EST_PRES is
Descripc ión en VHDL:
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case EST_PRES is
when E0 => if INIC=' 1' then EST_SIG <= E3;
elsif SUM=' 1' then EST_SIG <= E1;
else EST_SIG <= E0;
end if;
when E1 => if COUT=' 1' then EST_SIG <= E2;
else EST_SIG <= E3;
end if;
when E2 => if INIC=' 0' then EST_SIG <= E2;
else EST_SIG <= E3;
end if;
when E3 => if (INIC or SUM) = ' 1' then EST_SIG <= E3;
else EST_SIG <= E0;
end if;
end case;
end process ES;
Descripc ión en VHDL:
![Page 124: VHDL(Iniciar)](https://reader034.fdocuments.mx/reader034/viewer/2022042601/5452c5afb1af9f7c318b5308/html5/thumbnails/124.jpg)
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Descripc ión en VHDL:
REG: process (clk, resetL)
begin
if (resetL=' 0' ) thenEST_PRES<=E0;
elsif (clk' event) and (clk=' 1' ) then
EST_PRES<=EST_SIG;
end if;
end process REG;
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Descripc ión en VHDL:
LDRL <= ' 0' when EST_PRES=E1 else ' 1' ;
CLRL <= ' 0' when (EST_PRES=E1 OR EST_PRES =E0) AND INIC=' 1' else ' 1' ;
OVF1 <= ' 1' when EST_PRES=E1 AND COUT=' 1' else ' 0' ;
OVF0L <= ‘0' when (EST_PRES=E2 OR EST_PRES =E0) AND INIC=' 1' else ‘1' ;
ESTADO <= EST_PRES;
end UC;